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My Ph.D. dissertation research is focused on microarchitecture and compilation techniques for reducing the performance impact due to the following:
• complexity of centralized hardware structures,
• access delays due to the long wires interconnecting spatially separated resources,
• access delays due to requirements such as large number of ports, and bandwidth limitations associated with sharing of large centralized resources (register file and cache),
• phase-ordering problem in the code generation phase of compilers.

Clustered ILP processors try to solve the first three issues by partitioning the large centralized resources and grouping them into clusters, which communicate via shared inter-cluster buses or dedicated point-to-point buses.

Clustered ILP Processor architecture

Unfortunately, the phase-ordering problem, one of oldest open problems in back-end compiler design, is worse in the code generators for clustered ILP processors, making it one of the main performance limiting factors. My dissertation research provides a solution to this problem via a new code generation framework called CARS. I have also proposed two hardware structures in my dissertation besides CARS:
• a partitioned register file architecture and a fast code generation scheme to exploit it
• a distributed D-cache scheme.

© 2000 Krishnan Kailas
Last updated on $Date: 2000/08/22 03:02:00 $