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My PhD minor area is microelectronics;
these are some of the chips I designed for the various interesting digital and
analog VLSI courses at University of Maryland College Park during
1994-97. Some of these designs have been fabricated at
MOSIS and tested successfully.
- 8-bit bit-slice processor (HDL synthesis; the chip was fabricated and tested)
- 16-bit RISC CPU (HDL synthesis)
(Zhongying Zhang made an
enhanced
semi-full-custom version of it later, and then he went to Intel
to design slightly bigger chips :-).
- 16-bit CRC encoder/decoder (full-custom VLSI design; the chip was fabricated
and tested)
- 4-bit Wave Pipelined Carry Save Adder (SPICE simulation of
full-custom VLSI design).
Here's the project report
![[ps.gz]](psgz.gif)
(sorry, no figures!)